Memory cells of the stacked capacitor type are often employed in DRAMs (dynamic random access memories). But the memory cells of the stacked capacitor type do not have amplifying function, and with the reduction in the cell area, the signal charge quantity is decreased, and the signal voltage is lowered. As a solution thereto, gain cells which themselves have an amplifying function are employed. An example of such gain cells is described in (a) Nikkei Electronics (Oct. 7, 1985), pp. 262 to 266, and (b) H. Shichijo et al. "TITE RAM: A NEW SOI DRAM Gain Cell for Mbit DRAM's", Ext. Abs. 16th. Conf. on Solid State Devices & Materials, Kobe, 1984, pp. 265 to 268.
FIG. 1 and FIG. 2 show the structure and the circuit configuration of the gain cell described in these prior-art publications.
As illustrated, it comprises a polysilicon MOSFET (SOI MOSFET) 34 formed on an oxide film 32 and serving as a write transistor (switching transistor) and a bulk MOSFET 33 serving as a read transistor (sense transistor). The MOSFET 33 is formed to intersect the channel of the MOSFET 34. Since both transistors are of n-channel construction, the polycrystalline channel part may be either p-doped, non-doped or lightly n-doped. The gain cell is associated with write word lines (electrodes) 36 and 39, a read bit line 37, and a write bit line 40. A charge storage layer 35 is formed between the word line 36 and the read transistor 33.
For writing, the word lines 36 and 39 are made High, and the write bit line 40 is made to carry either "1" or "0". After the writing, the transistor 39 is kept off, and the charge storage layer 35 is electrically floating.
For reading, only the read word line 36 is made High, and the gate electrode potential of the read transistor 33 rises because of the capacitive coupling, and the potential on the read bit line 37 is either "1" or "0" depending on the data that has been stored on the charge storage layer 35.
Structure of the gain cell may be viewed as a combination of an EPROM element and a polysilicon transistor connected to the floating gate of the EPROM element.
The prior art memory device had a shortcoming in that each cell had to be connected to five interconnection conductors. This imposed a limitation to the increase in the degree of integration. Moreover, in reading operation, the ratio between capacitances is critical but since the capacitance depends on the area of the capacitor electrodes, this could not be highly accurate, and stable operation was not ensured.